Many caches, one memory
Each core has its own cache, so the same memory line can live in several caches at once. A cache coherence protocol ensures all these copies stay consistent, so a write by one core is eventually seen by all and no two caches disagree on a line's value.
The MESI states
MESI tracks each cached line in one of four states.
- Modified: this cache holds the only, dirty copy, and memory is stale.
- Exclusive: this cache holds the only, clean copy.
- Shared: several caches hold the same clean copy.
- Invalid: the line is not valid here.
How writes propagate
To write a line, a core must first own it in Modified or Exclusive, which requires sending an invalidate to other caches holding it. Those caches drop to Invalid. A later read by another core triggers a coherence miss that fetches the up to date value, possibly from the owning cache. Coherence guarantees a single value per line but says nothing about ordering across different lines, which is the separate job of the memory model.
Key idea
MESI keeps per core caches coherent by tracking Modified Exclusive Shared and Invalid states and invalidating other copies before a write, guaranteeing one value per line but not cross line ordering.