Transactions in silicon
Hardware transactional memory, or HTM, lets a thread mark a region of code as a transaction. The processor runs it speculatively, tracking every memory location it reads and writes. If no other core touches those locations conflictingly, the transaction commits atomically. Otherwise the hardware aborts it and the changes vanish.
How the CPU tracks conflicts
HTM piggybacks on the cache coherence protocol that already detects when cores share data.
- The transaction read set and write set live in cache, tagged transactional.
- A conflicting access from another core triggers a coherence event that aborts the transaction.
Because the buffer is the cache, a transaction that overflows the cache or hits an interrupt also aborts. HTM is therefore best effort, not guaranteed to ever succeed.
The fallback path
Since any transaction can abort for non conflict reasons, software must provide a fallback, usually a lock.
- Retry the transaction a few times.
- If it keeps failing, take a global lock and run the slow path.
Key idea
HTM uses cache coherence to run a code region atomically and abort on conflict, but because it is best effort it always needs a software lock fallback.