Why coherence is needed
Each core caches copies of memory lines. Without coordination two cores could hold different values for the same address. A cache coherence protocol keeps every cached copy consistent.
The four MESI states
Each cache line carries one of four states:
- Modified means this core has the only copy and it is dirty.
- Exclusive means this core has the only copy and it is clean.
- Shared means several cores may hold a clean copy.
- Invalid means the line holds no valid data.
How transitions work
When a core wants to write, it must move the line to Modified. To do that it sends an invalidate message so every other copy becomes Invalid. A read that misses can pull a clean copy and land in Shared or Exclusive.
These messages travel over the interconnect, so writes to shared lines are expensive. The protocol guarantees that at most one core can be in Modified at a time, which is what makes a single coherent value possible.
Key idea
MESI lets cores share memory safely by tracking each line as Modified Exclusive Shared or Invalid and invalidating others before a write.