A different atomic primitive
Many RISC processors offer atomicity through a pair rather than a single CAS. Load linked reads an address and quietly marks it as watched. Store conditional then writes a new value but succeeds only if no other write touched the address since the load linked.
How the pair works
- Load linked reads the value and starts a reservation on the line.
- The code computes a new value.
- Store conditional attempts the write. It succeeds if the reservation is intact and fails if any other core wrote the line.
- On failure the code loops and tries again.
Why it avoids ABA
Because the reservation is broken by any write to the line, not just a change in value, the pair detects an intervening A to B to A sequence that would fool a plain compare and swap. This sidesteps the ABA problem at the hardware level.
The cost is that reservations are fragile. A context switch or an unrelated nearby write can break them, causing spurious failures, so the retry loop must tolerate occasional false negatives.
Key idea
Load linked and store conditional give atomicity by reserving a line and committing only if no write intervened, which detects any intervening change and so avoids the ABA problem that troubles compare and swap.